Ateliers et séminaires 2009
|
Titre de l’animation |
type |
date |
durée |
Coordinateur(s) technique(s) |
|---|---|---|---|---|
|
Optical Localization Techniques Workshop |
A |
26-27 Janvier |
2 jours |
Philippe Perdu (CNES) |
| Electron-Surface Scattering, Electron-Grain Boundary Scattering And Charge Transport In Thin Metallic Films | S | 25 Février | 0,5 jour | Philippe Perdu (CNES) et CCT MAT |
| Comprendre les évolutions des technologies Silicium Journée du CCT MCE et AG |
S | 2 mars | 1 jour | Christian Moreau (CELAR) et Sebastien Salas (Captronic) |
| International Symposium On Reliability Of Optoelectronics For Space (ISROS) | A | 11-15 mai | 5 jours | Olivier Gilard (CNES) |
| Comprendre les évolutions des technologies Silicium (Paris) | A | 11 Juin | 1 jour | dominique talbourdet (EDF) |
| Caractérisation Micromécanique de matériaux en couche mince destinés aux micro- et nano- technologies | S | 17 Septembre | 0,5 jour | Cedric Seguinau (NovaMEMS) |
| Round table “Network on Chip” | A | 17-18 Septembre | 2 jours | Laurent Hili (ESA) |
| Atelier PMES “Power Micro-devices Embedded for Mobile Solutions, from energy harvesting to power management & supply” | A | 1 Octobre | 1 jour |
Clovis Lataste (NovaMEMS) Carole Rossi (LAAS) |
| Workshop on Long Term Reliability | A | 9 Octobre | 0,5 jour |
Philippe perdu (CNES) Laurent Cretinon (EDF) |
| stockage & retour d’expérience | A | 21 Octobre | 1 jour | Dominique Talbourdet (EDF) |
| IPDiA : solution d'intégration 3D | S | 3 Décembre | 0,5 jour | Philippe Perdu (CNES) |
| Obsolescence, comment l’éviter ou la gérer? | S | 3 Décembre | 1 jour | Myriam Cournet (CNES) |
| CMOS detectors for high performance applications | A | 8-9 Décembre | 2 jours | Alex Materne (CNES) |
Voici une brève synthèse des animations 2009 :
Optical Localization Techniques Workshop
The aim of this workshop is to cluster tool manufacturers and users in a unique opportunity to exchange information on optical techniques like emission microscopy (static, TRE, TRI, …), laser stimulation (thermal and photoelectric, static and dynamic) and laser voltage probing. It should allow deep technical exchanges on best practices on existing tools, new techniques to extend applications in order to increase return on investment, and new developments including tool manufacturer roadmaps to prepare the future.
It will be a workshop, not a conference, and a friendly event focused on practical issues. It will also give users a chance to meet main tool manufacturers and to foster their requirements for new tools and techniques.
les présentations (accès privatif):
- Introduction
- Static Emission microscopy
Static Emission microscopy background
InGaAs versus CCD
SIL for improved sensitivity and spatial resolution
Selecting Centric vs. Aplanatic RSIL
Influence of Temperature Variation on Electrical and Photon Emission AlGaN/GaN High Mobility Electron Transistors Characterization
- Optical probing techniques: Laser Voltage Probing, Time Resolved Emission & Time Resolved Imaging
Dynamic Emission microscopy background
Functional analysis with dynamic emission microscopy
Laser Timing Probe with Frequency Mapping
LVP Signal – Where to Probe? Modulation Mapping or LVI
Facing the poor optical resolution and the sensor sensitivity limitation challenges for TRE probing
Design visibility enhancement for failure analysis
- Static laser Stimulation
Nanoscale resolution options for optical localization techniques
Static Laser Stimulation background
3D resolution with MOBIRCH
Application of static laser stimulation to MEMS FA
Case studies using MTLS on FA daily products
Relationship of TLS/SIFT tools
- Thermography
Application of Thermography: some examples
Application of Lock-in Thermography for Defect Localisation at Opened and Fully Packaged Single- and Multi-chip Devices
Application of transient interferometric mapping (TIM) technique for analysis of ns-time scale thermal and carrier dynamics in ESD protection devices
High Resolution Raman Temperature Measurements
- Dynamic Laser Stimulation
Dynamic Laser Stimulation Background
Case studies in DLS at NXP Semiconductors
xVM applied to automotive products
Coupling Test and DLS
DLS using on-chip CPU:Harder, better, faster, stronger?
Application of dynamic laser stimulation for qualification purpose
Picosecond laser stimulation: status, applications & challenges
- Combined techniques
Design analysis in analog signal circuits enhanced by Emission Microscopy and laser based techniques
Failure Diagnosis by Optical Techniques Combined to Layout Localization Software for Wafer Yield Improvement
Multiple FA techniques on advanced technologies
Optical investigation of a resistance-change memory device
Electron-Surface Scattering, Electron-Grain Boundary Scattering And Charge Transport In Thin Metallic Films
Raúl C. Muñoz, professeur de physique (Universidad de Chile) est reconnu au niveau international pour ses travaux sur les couches minces métalliques. Que se soit pour les semi-conducteurs des technologies actuelles et futures, les micro ou les
nano systèmes, le comportement électrique de ces couches revêt une importance fondamentale. Les propriétés « classiques » sont elles préservées lorsque l’épaisseur de la couche ne fait plus que quelques nanomètres ? Que se passe t’il lorsque cette couche
présente un forte rugosité ? La conductivité est elle réduite ou améliorée ?
Nous n’avons pas souvent l’occasion d’avoir un exposé avancé sur ces questions et la présence du professeur Raúl C. Muñoz est une opportunité intéressante pour avoir une vision scientifique plus précise sur ces questions.
les présentations (accès privatif):
Comprendre les évolutions des technologies Silicium
Le but de ce tutorial est de fournir les clés pour comprendre l’évolution des technologies jusqu’au noeud technologie 65nm et de percevoir les enjeux pour les générations futures. Lors de l’analyse de défaillance ou de construction, il s’avère nécessaire de
bien intégrer le process pour pouvoir poser le bon diagnostic. Plus précisément, ce tutorial vous permettra de :
- Comprendre les clés de l’évolution.
- Percevoir les enjeux pour les générations futures.
- Comprendre les nouvelles briques technologiques.
- Pouvoir décrypter le langage des fondeurs.
- Percevoir les enjeux pour le Failure Analysis et les mécanismes de défaillance associés.
- Pouvoir maitriser les risques lors du choix d’une technologie
les présentations (accès privatif):
International Symposium On Reliability Of Optoelectronics For Space (ISROS)
The 2009 First International Symposium on Reliability of Optoelectronics For Space (ISROS 2009) and joint thematic day Radiation Effects On Optoelectronics (OPTORAD) were held in Cagliari (Italy) 11-15 May 2009.
The aim of this Symposium was to give the floor to engineers and researchers to address in an informal framework, their work in progress in the fields of qualification, evaluation, reliability assessment and failure analysis on optoelectronic devices for space applications.
Tutorial short courses were offered in conjunction with the Symposium by experts on several fields of optoelectronics.
The Symposium provided a productive and informal environment for a fruitful exchange of ideas. It featured a technical program consisting of several sessions dedicated to :
- Imagers : APSs, CCDs
- Emitters : laser diodes, light emitting diodes
- Photoreceivers : photodiodes, phototransistors, solar cells
- Optical functions : optical fibres, modulators, optical switches, ...
At the end of the Symposium, the thematic day, OPTORAD (OPTOelectronic devices – RADiation effects), sponsored by the RADECS association, offered invited papers treating on the effects of space radiations on optoelectronic devices.
A round table “OPTOELECTRONIC DEVICES FOR SPACE : NOW AND TOMORROW” was also organized during the conference. The discussions were centred around the following questions :
- In which application, optoelectronics based solutions may be used instead of other technologies ? Application related to telecommunication or observation satellites, scientific missions, long term extra Earth/Moon or Solar missions will be considered.
- What are the main optoelectronics devices of interest for these applications?
- Why did not the space application market use them in a deeper way yet?
- What could be done at manufacturers, space industries, space agencies, end-users and operators level to push these technologies?
les présentations (accès privatif):
- ISROS Flyer
- Agenda
- Space needs on optoelectronics
- Invited papers
- Tutorial
- Emitters
- Photodetector and Receiver Imagers
- Optical functions
- Posters
Caractérisation Micromécanique de matériaux en couche mince destinés aux micro- et nano- technologies
les présentations (accès privatif)
Round Table: Network on Chi
NoC paradigm has been an active field of research over the last decade. This field of research has grown with the necessity of higher design productivity and its corollary technology scale down (65nm, 45nm, 32nm, 22nm …). How can we maximize IP blocks reuse (plug & play) and how can we overcome some of the cumbersome aspects linked to bus topologies (place & route congestions, timing closure, signal integrity).
Through the various presentations given by Research Institutes and privates companies, the ESA-CNES round table had for objective to identify how existing solutions developed in Europe could potentially be adapted and transposed to the Space sector. What might be the benefit for ESA and CNES to invest in such a technology and what might be the delta efforts needed to mature this technology for Space applications.
les présentations (accès privatif):
Session 1: Introduction
- Welcome address (Philippe Armbruster, Head of Data System Division, ESA / The Netherlands)
- Why NoC for Space? (Philippe Perdu, CNES / France)
- ESA IPs & SoCs developments (Laurent Hili, ESA / The Netherlands)
- NoC tutorial (Ran Ginosar, Technion Institute of Technologies / Israel)
Session 2: Architectures part 1
- Asynchronous 3D NoCs (Hamed Sheibanyrad, Frederic Petrot, TIMA Laboratory / France)
- Supporting Distributed Shared Memory on Multi-core NoCs with a Dual Micro coded Controller (Axel Jantsch, KTH / Sweden)
- Generation of RTL-code and test facilities for on-chip TDM network (Geir Åge Noven, Kongsberg / Norway)
Session 3: Architectures part 2
- Using network-on-chip technology for creating scalable programmable many-core system-on-chip architectures (Gerard Rauwerda, Recore Systems / The Netherlands)
- NoC concepts with XPP-III (Eberhard Schuler, PACT / Germany)
- Spidergon STNoC, the Interconnect Processing Unit (IPU) (Riccardo Locatelli, ST microelectronics / France)
- The Real-Time Network on Chip Aethereal (including comparison with SpaceWire) (Kees Goossens, SOC Architectures and Infrastructure NXP Semiconductors / The Netherlands)
- SoCWire: a SpaceWire inspired fault tolerant Network on Chip approach for reconfigurable System on Chip in Space applications (Bjorn Osterloh, Braunschweig Institute of Computer and Communication Network Engineering / Germany)
- HOST (Hardware Operating System Technology) (Steve Parkes, University of Dundee / UK)
Session 4: Tools and design methodologies
- Link between NoC Technology and programming model in a reconfigurable System on Chip (Domique Houzet, Institut National Polytechnique Grenoble / France)
- A Theorem-Proving Based Approach for the Formal Verification of NoCs (Laurence Pierre, TIMA Laboratory / France)
- OCCN and Virtual Platform for power estimation and fault tolerant routing (Constantin Papadas, ISD / Greece)
Session 5: Fault tolerant NoCs
- Multi-level fault tolerance in 2D and 3D NoCs (Claudia Rusu, TIMA Laboratory / France)
- Concepts for Robust NoC Communication (Martin Radetzki, Stuttgart University / Germany)
Session 6: Space applications
- From SoC to NoC based on SCOC3 HW & SW developments (Marc Souyri, Jean-François Coldefy, Franck Koebel, Vincent Lefftz, Astrium / France)
Session 7: Conclusion
- Round table synthesis note (Laurent Hili, ESA / The Netherlands)
Power Micro-devices Embedded for Mobile Solutions, from energy harvesting to power management & supply
Cet atelier a abordé les différentes solutions de récupération, gestion et stockage d’énergie destinées aux systèmes embarqués, et tout particulièrement aux réseaux de capteurs sans fils
les présentations (accès privatif):
Round Table: Network on Chi
NoC paradigm has been an active field of research over the last decade. This field of research has grown with the necessity of higher design productivity and its corollary technology scale down (65nm, 45nm, 32nm, 22nm …). How can we maximize IP blocks reuse (plug & play) and how can we overcome some of the cumbersome aspects linked to bus topologies (place & route congestions, timing closure, signal integrity).
Through the various presentations given by Research Institutes and privates companies, the ESA-CNES round table had for objective to identify how existing solutions developed in Europe could potentially be adapted and transposed to the Space sector. What might be the benefit for ESA and CNES to invest in such a technology and what might be the delta efforts needed to mature this technology for Space applications.
les présentations (accès privatif):
Session 1: Introduction
- Welcome address (Philippe Armbruster, Head of Data System Division, ESA / The Netherlands)
- Why NoC for Space? (Philippe Perdu, CNES / France)
- ESA IPs & SoCs developments (Laurent Hili, ESA / The Netherlands)
- NoC tutorial (Ran Ginosar, Technion Institute of Technologies / Israel)
Session 2: Architectures part 1
- Asynchronous 3D NoCs (Hamed Sheibanyrad, Frederic Petrot, TIMA Laboratory / France)
- Supporting Distributed Shared Memory on Multi-core NoCs with a Dual Micro coded Controller (Axel Jantsch, KTH / Sweden)
- Generation of RTL-code and test facilities for on-chip TDM network (Geir Åge Noven, Kongsberg / Norway)
Session 3: Architectures part 2
- Using network-on-chip technology for creating scalable programmable many-core system-on-chip architectures (Gerard Rauwerda, Recore Systems / The Netherlands)
- NoC concepts with XPP-III (Eberhard Schuler, PACT / Germany)
- Spidergon STNoC, the Interconnect Processing Unit (IPU) (Riccardo Locatelli, ST microelectronics / France)
- The Real-Time Network on Chip Aethereal (including comparison with SpaceWire) (Kees Goossens, SOC Architectures and Infrastructure NXP Semiconductors / The Netherlands)
- SoCWire: a SpaceWire inspired fault tolerant Network on Chip approach for reconfigurable System on Chip in Space applications (Bjorn Osterloh, Braunschweig Institute of Computer and Communication Network Engineering / Germany)
- HOST (Hardware Operating System Technology) (Steve Parkes, University of Dundee / UK)
Session 4: Tools and design methodologies
- Link between NoC Technology and programming model in a reconfigurable System on Chip (Domique Houzet, Institut National Polytechnique Grenoble / France)
- A Theorem-Proving Based Approach for the Formal Verification of NoCs (Laurence Pierre, TIMA Laboratory / France)
- OCCN and Virtual Platform for power estimation and fault tolerant routing (Constantin Papadas, ISD / Greece)
Session 5: Fault tolerant NoCs
- Multi-level fault tolerance in 2D and 3D NoCs (Claudia Rusu, TIMA Laboratory / France)
- Concepts for Robust NoC Communication (Martin Radetzki, Stuttgart University / Germany)
Session 6: Space applications
- From SoC to NoC based on SCOC3 HW & SW developments (Marc Souyri, Jean-François Coldefy, Franck Koebel, Vincent Lefftz, Astrium / France)
Session 7: Conclusion
- Round table synthesis note (Laurent Hili, ESA / The Netherlands)
IPDiA : solution d'intégration 3D
Les domaines techniques couverts dans les présentations faites par la société IPDiA sur ses activités sont ceux de l'intégration des passifs (intégration 3D dans le silicium, bénéfices d'une technologie en termes de miniaturisation et de performances applicatives) et la miniaturisation des applications (interposers en silicium avec "TSV" : Through Silicon Via, miniaturisation du packaging avec wafers amincis, technologies d'interconnections fines par bumping, approches SiP sur plateforme à base d'IPD, technologies IPD enterrées: Embedded die).
les présentations (accès privatif):
Obsolescence, comment l’éviter ou la gérer?
les présentations (accès privatif):
- Introduction de la journée (P. Perdu, M. Cournet, CNES)
- Présentation de la problématique obsolescence vue des fabricants de composants (V. Gambolati, STM)
Solutions préventives
- Mise en place d'indicateurs pour l'évaluation et la maîtrise des risques, Méthodologie de développement d'un produit pérenne (D. Polisset, SERMA)
- L’Obsolescence, comment la gérer? Présentation du processus Observatoire Obsolescence (G. Guffroy, ACTIA)
- La pratique de la Gestion des Risques d'Obsolescence à la DGA (M. Thuault, DGA)
Solution curative avant dépassement du Last Buy Order : le stockage stratégique
- Mécanismes de dégradation des composants et des cartes en stockage longue durée (O. Maire, EADS IW)
- Conditions de stockage des composants et des cartes (mise à jour du guide UTE C 96029), stratégie de stockage (D. Talbourdet, EDF)
- Méthodologie de dimensionnement des stocks en vue de la production et en vue du maintien en conditions opérationnelles (F. Davenel, DGA)
Solutions curatives après dépassement du Last Buy Order
- Risques liés à l'approvisionnement de composants obsolètes : la contrefaçon (D. Standarovski, CNES)
- Obsolete components procurement (P. Green, ROCHESTER)
- Reconstruction d’hybrides, réencapsulation (JP Berger, SDTIE Elmo)
- Redesign de semiconducteurs (Y. Robert, IDMOS)
Retours d’Expérience
- Retour d’expérience d’EDF (D. Talbourdet, EDF)
- Retour d’expérience d’Airbus (P. Heins, AIRBUS)
CMOS detectors for high performance applications
les présentations (accès privatif):
Files:
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Titre de l’animation type date durée Coordinateur(s) technique(s) Optical Localization Techniques Workshop A 26-27...
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Titre de l’animation type date durée Coordinateur(s) technique(s) retour d’expérience sur l’...
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Titre de l’animation type date durée Coordinateur(s) technique(s) Tutorial sur les composants SOI S 27 avril 2007...
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Titre de l’animation type date durée Coordinateur(s) technique(s) Stimulation laser pulsé de composants...
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Titre de l’animation type date durée Coordinateur(s) technique(s) La durée de vie des composants é...
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